The Camera Link interface standard is a well established vision interface. The latest version of the standard — Version 2.0 — consolidates previous updates including Mini Camera Link connectors, Power over Camera Link (PoCL), PoCL-Lite (a smaller minimized PoCL interface) and the Camera Link cable specification.
Originally based on the National Semiconductor interface Channel-link chip set, the Camera Link standard provides five different levels of implementation, ‘Lite’, ‘Medium’ and ‘Full’ and 80-bit mode (often called Deca). The maximum data transfer rate supported by Camera Link, using 80 bit mode, is 850 MB/sec, using three chipsets.
At the forum, Reynold Dodson, the President of BitFlow, acknowledged the fact that the sheer maturity of the standard has created certain compatibility issues that the Camera Link committee is working to resolve.
Notably, the specification itself originally demanded that designers implemented the Camera Link physical interface using the National Semiconductor chipset. Today, however, many designers have eschewed the use of the older chip set by designing their own Channel Link interface inside an FPGA in order to reduce costs.
The burning issue for the Camera Link committee is how to determine whether products that incorporate proprietary Channel Link interfaces are actually now Camera Link compliant, and how best to test them. To do so, Dodson says that the committee is currently developing a software test suite that will enable the compatibility of a variety of Camera Link hardware products — such as FPGAs — to be validated.